This invention pertains to fabrication of electronic devices such as integrated circuits; more specifically, this invention relates to methods and formulations for cleaning substrates prior to electroless deposition of cap layers on metal and dielectric damascene metallization structures.
The cleaning process for patterned substrates prior to electroless deposition of cap layers on metal interconnects such as copper interconnects is crucial for electroless plating processes. A clean substrate surface is needed to ensure good deposition selectivity, low defect counts, and low etching of the metal interconnect. Using copper technology as an example, the surface of the patterned substrates includes copper interconnect structures embedded in a dielectric, i.e., damascene or dual damascene structures, formed in part by chemical mechanical planarization (CMP). The cap layer is deposited on the copper after CMP. Examples of materials for the cap layer are materials such as cobalt, cobalt alloy, cobalt tungsten, cobalt-nickel alloy, nickel, and nickel alloy. There are many post-CMP cleaning solutions used for cleaning patterned substrates prior to electroless deposition of the cap layer. However, the goals of post-CMP cleaning and the goals of cleaning for electroless deposition of the cap layer are not the same. Consequently, post-CMP cleaning solutions may not produce the type of clean surface needed for electroless deposition of high-quality cap layers. For instance, many of the standard technology cleaning solutions remove only the outer oxide (cupric oxide) film from the copper surface while leaving the inner, mostly cuprous oxide, intact on the surface to passivate the copper. Another common approach attempts to minimize copper etching by including copper corrosion inhibitors in the post-CMP clean solution. Some of the corrosion inhibitors or the copper oxide, if left on the surface before electroless plating, can create significant problems for the electroless deposition process such as causing no or spotty plating on the copper, formation of pinholes/pits in the cap layer, poor adhesion between the substrate and the cap layer, or extra cap layer deposition on the dielectric.
There is a need for improved processes and solutions for depositing cap layers on substrates used to fabricate devices such as electronic devices. More specifically, there is a need for improved cleaning solutions and methods of cleaning substrates that can produce contamination and defect free substrate surfaces for electroless deposition of cap layers that can be used to meet the performance and manufacturing requirements for such devices.